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Heidenhain Controller
Drive · Intermediate · 30-120 minutes
HEIDENHAIN 330-0016 - CC inverter for spindle RDY=1
This alarm is fundamentally a handshake mismatch between the TNC control's expectation of spindle inverter status and the actual ready signal being reported by the CC inverter module. The TNC receives an unexpected RDY=1 signal, usually because the PLC enable sequence hasn't been properly synchronized with the drive state, or there's a timing/hardware fault in the ready signal feedback path from the CC to the control.
HEIDENHAIN 330-0016 - CC inverter for spindle RDY=1
CC inverter for spindle RDY=1
An error occurred during initialization or cyclic operation of the internal I/O hardware. This affects communication with SPI modules.
Root Cause Summary
This alarm is fundamentally a handshake mismatch between the TNC control's expectation of spindle inverter status and the actual ready signal being reported by the CC inverter module. The TNC receives an unexpected RDY=1 signal, usually because the PLC enable sequence hasn't been properly synchronized with the drive state, or there's a timing/hardware fault in the ready signal feedback path from the CC to the control.
Safety
Causes and Fixes
Access PLC program
Press MOD key, select 'PLC', then 'Program'. Navigate to the spindle handling section (typically marked with comments like 'SPINDLE CC2' or 'S2 ENABLE').
Look for marker names like M_CC2_ENABLE (output) and I_CC2_RDY (input) - the naming convention varies by machine builder but follows this pattern.
Check enable-to-ready logic
Verify that the output enable signal to CC%2 is set TRUE before checking the ready input, and that ready monitoring doesn't begin until after enable is commanded. There should be a delay or state machine handling the transition.
Do not modify PLC logic without backing up the current program via MOD > PLC > Backup.
Monitor PLC markers in real-time
Go to MOD > PLC > Status. Filter for CC2 or spindle-related markers. Perform an E-STOP reset and observe the sequence: enable output should go high, then after a brief delay (typically 100-500ms), ready input should go high.
Use the 'Trace' function in PLC Status to capture the exact timing of signal transitions - this reveals race conditions.
Correct the PLC logic
If the sequence is incorrect, modify the PLC program to add proper state management or timer delays. Typical fix involves adding a T (timer) element between enable output and ready monitoring, or implementing a state machine with WAIT conditions.
Test PLC changes in single-step mode first (MOD > PLC > Test mode) before running in automatic.
Call a technician if:
Prevention
Common Mistakes
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